EAI 805-Embedded AI Hardware
Course Description
EAI 805 is a hardware-centric core course on Embedded Artificial Intelligence, delivered here as an eight-week fundamentals programme. It studies the architectures, communication channels, processing elements, memory systems, sensors, and power-management techniques that enable AI inference at the edge; surveys and contrasts the main embedded-AI hardware platforms in the market (CPUs, GPUs, TPUs, FPGAs, and ACAP-class devices); introduces the core toolchain (Vivado, Vitis HLS, and the PYNQ Python framework); and applies these concepts through weekly practicals on the AMD/Xilinx PYNQ-Z2 board. The course concentrates on fundamentals and closes with a single integrated case study of an accelerated computer-vision workload, emphasising the hardware/software boundary. Advanced acceleration internals, deep parallelism and power/quantization optimisation, hardware/software co-design analysis, and full multi-toolchain deployment are deferred to the extended version of the course.
Learning Outcomes
On successful completion of this course, the student should be able to:
- Describe the characteristics of embedded AI hardware and contrast major platforms (CPU, GPU, TPU, NPU, FPGA) by performance, power, and cost.
- Explain the internal architecture and on-chip communication of heterogeneous SoCs, particularly the Xilinx Zynq-7000 family.
- Configure and program the PYNQ-Z2 platform using Vivado, Vitis HLS, and the PYNQ Python framework to build a simple custom hardware accelerator.
- Identify the main embedded-AI toolchains and explain, at a survey level, how a trained neural network is deployed onto an FPGA-based platform.
- Describe the role of processing elements, the memory hierarchy, sensors, and power management in embedded AI systems.
- Analyse basic hardware/software trade-offs and integrate the components of a simple embedded AI vision pipeline on the PYNQ-Z2.
Course Flow Overview
The eight weeks are organised in three progressive blocks that map directly onto the course content:
- Block A (Weeks 1–3): Foundations — what embedded AI hardware is, heterogeneous SoC architecture and on-chip communication, and how the major platforms compare.
- Block B (Weeks 4–5): Hardware components — processing elements, memory organisation, sensors, and power management.
- Block C (Weeks 6–8): Toolchain, programming, and integration — the core FPGA toolflow at survey level, programming the PYNQ-Z2 in Python and C++, and a single integrated case study with course review.
- Digital logic and computer architecture fundamentals
- working knowledge of Python and C++
- and basic familiarity with machine learning (convolutional neural networks). Prior exposure to Verilog/VHDL is helpful but not required.
- 8 Sections
- 27 Lessons
- 8 Weeks
- Introduction to Embedded AI HardwareWhat distinguishes Embedded AI hardware from general computing; characteristics (real-time, energy-constrained, deterministic); ecosystem map — MCUs, MPUs, GPUs, TPUs, FPGAs, ACAPs, NPUs; the inference-vs-training distinction; survey of application domains (vision, audio, robotics, healthcare, industrial).6
- Embedded System Architecture and Internal Communication ChannelsHeterogeneous SoC architecture; Zynq-7000 PS/PL split (dual Cortex-A9 + Artix-7 FPGA); AMBA AXI4 / AXI4-Lite / AXI4-Stream protocols; on-chip interconnects; memory-mapped vs streaming interfaces; DMA.8
- Comparison of Embedded AI Hardware PlatformsQuantitative comparison axes: TOPS/W, latency, area, $/TOPS, model-size limits; CPU (ARM Cortex), GPU (Jetson), TPU (Coral Edge TPU), MCU+NPU (Arm Ethos-U55), FPGA (Zynq-7000, Zynq UltraScale+); roofline analysis; choosing a platform for a given workload.8
- Processing Elements and Memory Organisation1
- Sensors, Interfaces, and Power Management1
- The Toolchain for Embedded AI Hardware (Survey)1
- Programming Embedded AI Hardware: Python and C++1
- Integration, Case Study & Course Review1
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